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Low Power Consumption Tunnel Transistors
Realizing next-generation energy-saving devices with new semiconductor interfaces
With this research we proposed and realized an unprecedented low-power FET/tunnel FET by applying a new semiconductor solid-phase interface, which is formed by very small nanowires a few thousandths of a hair’s width, to a switch element.
Research
High performance of microprocessors and semiconductor integrated circuits, which are the brains of smartphones and PCs, have been achieved by reducing the size of field-effect transistors (FETs), which are the basic elements, and installing approximately 2 to 3 billion of them. While higher performance is being achieved, the rapid increase in power consumption of these FETs is becoming a serious problem. This is because there is a physical limit (60 mV/digit) on the switching performance (sub-threshold factor) of FETs. To realize drastic energy saving in the future, it is necessary to develop a new switch element that can break through the physical limit on FETs and their practical application. With this research, we have proposed and realized an unprecedented low-power-consumption tunnel FET.
Katsuhiro Tomioka Associate Professor
